Electronic structures such as multilayered printed circuit boards (PCBs), laminate chip carriers, and the like permit formation of multiple circuits in a minimum volume or space. These structures typically comprise a stack of layers of signal, ground and/or power planes (lines) separated from each other by a layer of dielectric material. The lines are often in electrical contact with each other by plated holes passing through the dielectric layers. The plated holes are often referred to as “vias” if internally located, “blind vias” if extending a predetermined depth within the board from an external surface, or “plated thru-holes” (PTHs) if extending substantially through the board's full thickness. By the term “thru-hole” as used herein is meant to include all three types of such board openings.
Presently known methods of fabricating PCBs, chip carriers and the like typically comprise fabrication of separate inner-layer circuits (circuitized layers), which are formed by coating a photosensitive layer or film over a copper layer of a copper clad inner-layer base material. The photosensitive coating is imaged, developed and the exposed copper is etched to form conductor lines. After etching, the photosensitive film is stripped from the copper leaving the circuit pattern on the surface of the inner-layer base material. This processing is also referred to as photolithographic processing in the PCB art and further description is not deemed necessary.
Following the formation of individual inner-layer circuits, a multilayer stack is formed by preparing a lay-up of inner-layers, ground planes, power planes, etc., typically separated from each other by a layer of dielectric pre-preg material, the latter typically comprising a layer of glass (typically fiberglass) cloth impregnated with a partially cured material, typically a B-stage epoxy resin. The top and bottom outer layers of the stack usually comprise copper clad, glass-filled, epoxy planar substrates with the copper cladding comprising exterior surfaces of the stack. The stack is laminated to form a monolithic structure using heat and pressure to fully cure the B-stage resin. The stack so formed typically has metal (usually copper) cladding on both of its exterior surfaces. Exterior circuit layers are formed in the copper cladding using procedures similar to the procedures used to form the inner-layer circuits. A photosensitive film is applied to the copper cladding. The coating is exposed to patterned activating radiation and developed. An etchant is then used to remove copper bared by the development of the photosensitive film. Finally, the remaining photosensitive film is removed to provide the exterior circuit layers.
The aforementioned electrically conductive thru-holes (or interconnects) are used to electrically connect individual circuit layers within the structure to each other and to the outer surfaces, and typically pass through all or a portion of the stack. Thru-holes are generally formed prior to the formation of circuits on the exterior surfaces by drilling holes through the stack at appropriate locations. Following several pre-treatment steps, the walls of the holes are catalyzed by contact with a plating catalyst and metallized, typically by contact with an electroless or electrolytic copper plating solution to form conductive pathways between circuit layers. Following formation of the conductive thru-holes, exterior circuits, or outer layers are formed using the procedure described above.
Following substrate construction, chips and/or other electrical components are mounted at appropriate locations on the exterior circuit layers of the multilayered stack, typically using solder mount pads to bond the components to the PCB. The components are often in electrical contact with the circuits within the structure through the conductive thru-holes, as desired. The solder pads are typically formed by coating an organic solder mask coating over the exterior circuit layers. The solder mask may be applied by screen coating a liquid solder mask coating material over the surface of the exterior circuit layers using a screen having openings defining areas where solder mount pads are to be formed. Alternatively, a photoimageable solder mask may be coated onto the board and exposed and developed to yield an array of openings defining the pads. The openings are then coated with solder using processes known to the art such as wave soldering.
Product complexity has increased significantly over the past few years. For example, PCBs for mainframe computers may have as many as 36 layers of circuitry or more, with the complete stack having a thickness of as much as about 0.250 inch (250 mils). These boards are typically designed with three or five mil wide signal lines and twelve mil diameter thru-holes. For increased circuit densification in many of today's electronic products such as PCBs, chip carriers and the like, the industry seeks to reduce signal lines to a width of two mils or less and diameters to two mils or less.
One important requirement of finished PCBs, chip carriers and the like is that the circuitized substrate cannot have exposed external conductors along the sides (edge portions) thereof, as opposed to the upper and/or lower substantially planar surfaces on which various electronic components such as electronic modules, capacitors, resistors, etc. (in the case of a PCB) are mounted. In the case of a chip carrier (which is typically also mounted on a PCB surface), one such surface is usually designed to accommodate a semiconductor chip and the other designed for connectors (e.g., pins, or conductive pads if solder balls are to couple this to an underlying PCB). These surfaces, understandably, include several conductors such as copper mounting pads, exposed signal lines, etc. prior to final assembly. However, the narrower sides (e.g., as thick as 0.250 inch in the above example) are typically not used for having such components electrically coupled thereto. Most importantly, however, such a requirement for no exposed electrical conductors (such as an exposed surface of an internal power or signal plane) is imposed on the industry by Underwriters Laboratory (U.L.) for both safety and functional reasons. These resulting products cannot include exposed conductive portions that might cause an electrical shock to an assembler or other substrate handler, as well as to the final user (e.g., in the case of a computer, the computer assembler and possibly the computer user himself/herself), and/or which might cause malfunction of the substrate due to electrical shorting, e.g., to an adjacent conductor on a connector designed to receive and hold the product (if a PCB) in place or to another, adjacent electronic component (if a chip carrier mounted on a PCB) adjacent such a component or other conductive element).
In U.S. Pat. No. 6,288,906, issued Sep. 11, 2001, there is described a method of making a multi-layer printed circuit board that includes power planes for its outer conductive layers. The outer conductive layers are patterned to accept circuitry, such as integrated circuits and surface mount devices. Mounting pads are provided on the outer conductive layers which include plated-through vias (holes) for electrical interconnection with other conductive layers of the board.
In U.S. Pat. No. 5,912,809, issued Jun. 15, 1999, the electrical potentials and very high frequency (VHF) currents in a circuit board are controlled by patterning the power plane of a multiple layered, capacitive plane printed circuit board in selected geometric patterns. The selected geometric patterns, both simple and complex, control voltages and currents by channeling the capacitance capacity for usage directed to a particular integrated circuit or circuits, isolated to a particular integrated circuit or circuits, or shared between integrated circuits.
In U.S. Pat. No. 5,685,070, issued Nov. 11, 1997, there is described a method of making a printed circuit board or card for direct chip attachment that includes at least one power core, at least one signal plane that is adjacent to the power core, and plated thru-holes for electrical connection is provided. In addition, a layer of dielectric material is adjacent the power core and a circuitized conductive layer is adjacent the dielectric material, followed by a layer of photosensitive dielectric material adjacent the conductive layer. Photodeveloped blind vias for subsequent connection to the power core and drilled blind vias for subsequent connection to the signal plane are provided.
In U.S. Pat. No. 5,418,689, issued May 23, 1995, there is described a method of making a printed circuit board for direct chip attachment that includes at least one power core, at least one signal plane adjacent the power core, and plated thru-holes for electrical connection. In addition, a layer of dielectric material is adjacent the power core and a circuitized conductive layer is adjacent the dielectric material, followed by a layer of photosensitive dielectric material adjacent the conductive layer.
In U.S. Pat. No. 5,384,433, issued Jan. 24, 1995, there is described a method of making a printed circuit board that includes an array of conductive pads including component-mounting holes disposed on first and second surfaces thereon. An array of conductive attachment lands arranged in pairs of first and second attachment lands are disposed on the first and second surfaces. The first and second attachment lands are insulated from one another and separated by a distance selected to allow attachment of standard sized components therebetween on the first and second surfaces of said circuit board. First and second conductive power distribution planes are disposed on the first and second surfaces and are insulated from the conductive pads and the second attachment lands disposed thereon.
Other methods of making circuitized substrates (namely PCBs) are described in the following U.S. Patents:
5,488,540Hatta5,736,796Price et al6,204,453Fallon et al6,418,031Archambeault et al6,557,154Harada et al
As described herein, the present invention represents a significant improvement over known processes, including those described above, used in the production of circuitized substrates such as PCBs. One particularly significant feature of this invention is the provision of a conductive layer such as a power core with a formed edge that is electrically isolated through the use of dielectric material which forms a protective barrier between the substrate's final outer edge portion and the conductive layer's edge.
It is believed that such an invention will represent a significant advancement in the art.